The present invention relates to a phase locked loop.
A phase locked loop (PLL) is a phase coupled control circuit, which is often used in electronic circuits, in particular for clock synchronisation. Conventionally, an integrated electronic circuit is called PLL, which constitutes essentially a controlled oscillator, if a phase coupled control loop is used in order to synchronize a reference frequency.
In particular in telecommunication appliances, phase locked loops are utilized in order to convert an input signal having a low frequency into an output signal having a high frequency. The output frequency of the phase locked loop should conventionally be an integer multiple of the input frequency. It is desired to generate a low noise high frequency output signal having a predetermined frequency.
The conventional phase locked loops include a phase comparator PFD, a voltage controlled oscillator VCO and a feed back loop running from the output 20 of the voltage controlled oscillator VCO to the input 10b of the phase comparator PFD; see FIG. 1. A frequency divider FD is provided in the feedback loop. The frequency divider divides the frequency of the feed back signals from the oscillator VCO by an integer N. The phase comparator compares the feed back signal with a periodic clock signal fed to an input 10a. The output of the phase comparator is a measure for the size of the phase difference between the feedback signal and the input periodic clock signal. Once an equilibrium state is reached, the phase and therefore also the frequency of the input signals of the phase comparator are equal. The output frequency of the voltage controlled oscillator must therefore be equal to N-times the frequency of the input clock signal.
The phase locked loop (PLL) must be designed in such a way, that the control loop reaches a stable equilibrium as fast as possible. If the output frequency of the voltage controlled oscillators deviate only by a small amount from the reference frequency, then the oscillator is readjusted. If the readjustment is too strong, then a negative phase difference at the input of the phase comparator may turn into a positive phase difference or vice versa. Instead of reaching a stable state, the control loop begins to oscillate. This means that the frequency of the output signal of the voltage control oscillator does not reach an essentially stable unaltered value; instead it oscillates about the reference frequency of the input signal of the phase locked loop. In order to prevent this, the charge pump CP and the filter LF are arranged between the output of the phase comparator PFD and the input of the voltage control oscillator. Readjustment occurs in a very fast succession (i.e. the control frequency is very high). These high control frequencies are suppressed by a low pass filter and consequently a small tolerance region is realized. The phase locked loop reaches a stable equilibrium after a while.
The charge pump outputs a current signal corresponding to the output of the phase comparator to the low pass filter LF. The low pass filter includes a resistor R, which is connected in serious with a capacitor C1. An additional capacitor C2 may be connected in parallel to the resistor and the capacitor C1. The second capacitor is not necessary for stabilising the phase locked loop. The low pass filter is essentially an integrator, which smoothes the signal from the charge pump. The resistor provides for an additive proportional amplification of the input current.
The disadvantage of the conventional phase locked loop is its noise, which is inevitably generated by the plurality of its noise sources. In particular, the low pass filter LF introduces noise components to the input signal of the voltage controlled oscillator. The main noise sources are depicted by the reference signs 30, 40 and 50 in FIG. 1. It is assumed, that the noise is added to the proper signal. Therefore, the noise sources are depicted as adders, which are connected to the actual components CP, LF and VCO. The noise of the charge pump is symbolized by the adder 30 in FIG. 1. Reference sign 40 represents the addition of noise of the low pass filter LF to the output signal of the low pass filter LF. Reference sign 50 represents the noise of the voltage controlled oscillator. Each noise source contributes to the overall noise in different frequency areas. The noise of the charge pump is a low frequency noise; the noise of the voltage controlled oscillator is high frequency noise. The low pass filter generates noise in an intermediate frequency region.
The noise from the voltage controlled oscillator is essentially filtered by the low pass filter and therefore does not pose great problems. If it is desired to provide a phase locked loop, which may process input signals having a wide frequency band width, then the noise of the charge pump CP and of the low pass filter LF is problematic. The output current of the charge pump could be increased as a counter measure against noise. The amplitude of the noise of the charge pump would be reduced in relation to the amplitude of the current. However, it is disadvantages, that the power consumption of the phase locked loop is considerably increased. Furthermore, the current may not be increased indefinitely without influencing the residual components such as the low pass filter. The noise could be suppressed by reducing the resistance R of the low pass filter. As a result, the band width of the phase locked loop is reduced. The band width relates to the allowed frequency region for the periodic clock signal at input 10a of the phase comparator. If the frequency of the clock signal lies outside of the frequency band width, then the phase locked loop does not reach a stable equilibrium state.
For these and other reasons, there is a need for the present invention.